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Team
Positions: 02
Minimum 5-8 years of experience in working with SoC Verification.
Experience in HVL System Verilog and verification methodology UVM.
Hardware software co-verification.
Post Silicon Debug and Validation.
Experience in verification of complex digital SoC designs with ARM CPUs/DSPs.
Programming language C, C++ and concepts of OOP’s.
Familiar with TLM model development.
Version control tools such as Clearcase/Git.
Scripting Languages Perl/Python/Shell/Tcl.
Positions: 02
Minimum 5-8 years of experience in ASIC/FPGA verification.
Experience in HVL System Verilog and verification methodology UVM, OVM & VMM.
Test plan development, Execution, Functional and Code coverage.
EDA Simulation tools Questasim/ NCSim / VCS.
Post Silicon Debug and Validation.
Programming language C, C++ and concepts of OOP’s.
Version control tools like CVS/ SVN/ Clear case/Perforce
Scripting Languages Perl/Python/Shell/Tcl.
Excellent written and verbal communication skills in English.
